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CDP1823C/3
March 1997
High-Reliability CMOS 128-Word x 8-Bit Static RAM
Description
The CDP1823C/3 is a 128 word x 8-bit CMOS/SOS static random access memory. It is compatible with the CDP1802, CDP1804, CDP1805, and CDP1806 microprocessors, and will interface directly without additional components. The CDP1823C has a recommended operating voltage range of 4V to 6.5V. The CDP1823C memory has 8 common data input and data output terminals for direct connection to a bidirectional data bus and is operated from a single voltage supply. Five chip select inputs are provided to simplify memory system expansion. In order to enable the CDP1823C, the chip select inputs CS2, CS3, and CS5 require a low input signal, and the chip select inputs CS1 and CS4 require a high input signal. The MRD signal enables all 8 output drivers when in the low state and should be in a high state during a write cycle. After valid data appear at the output, the address inputs may be changed immediately. Output data will be valid until either the MRD signal goes high, the device is deselected, or tAA (access time) after address changes.
Features
* For Applications in Aerospace, Military, and Critical Industrial Equipment * Compatible with CDP1800-Series Microprocessors at Maximum Speed * Interfaces with CDP1800-Series without Additional Components * Fast Access Time * At VDD = 5V, +25oC . . . . . . . . . . . . . . . . . . . . . . . . 275ns * Single Voltage Supply * Common Data Inputs and Outputs * Multiple Chip Select Inputs to Simplify Memory System Expansion * High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of VDD * Memory Retention for Standby Battery Voltage Down to 2V at 25oC * Latch-Up-Free Transient Radiation Tolerance Microprocessors
Ordering Information
PACKAGE SBDIP TEMP. RANGE PART NUMBER (5V) PKG. NO. D24.6
-55oC to +125oC CDP1823CD3
Pinout
CDP1823C/3 (SBDIP) TOP VIEW
BUS 0 BUS 1 BUS 2 BUS 3 BUS 4 BUS 5 BUS 6 BUS 7 CS1 1 2 3 4 5 6 7 8 9 24 VDD 23 A0 22 A1 21 A2 20 A3 19 A4 18 A5 17 A6 16 MWR 15 MRD 14 CS5 13 CS4
CS2 10 CS3 11 VSS 12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
2982.1
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CDP1823C/3
OPERATIONAL MODES FUNCTION Read Write Standby Not Selected MRD 0 1 1 X X X X X MWR X 0 1 X X X X X CS1 1 1 1 0 X X X X CS2 0 0 0 X 1 X X X CS3 0 0 0 X X 1 X X CS4 1 1 1 X X X 0 X CS5 0 0 0 X X X X 1 BUS TERMINAL STATE Storage State of Addressed Word Input High Impedance High Impedance High Impedance
NOTE: 1. Logic 1 = High, Logic 0 = Low, X = Don't Care.
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CDP1823C/3
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1823C/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .10mA
Thermal Information
Thermal Resistance (Typical) JA (oC/W) JC (oC/W) SBDIP Package . . . . . . . . . . . . . . . . . . 60 17 Maximum Operating Temperature Range (TA) . . . .-55oC to +125oC Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC Maximum Lead Temperature (During Soldering) . . . . . . . . . +265oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150oC
Recommended Operating Conditions
At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: LIMITS
PARAMETER Supply Voltage Range Recommended Input Voltage Range VDD = 5V 5% CONDITIONS
MIN 4 VSS
MAX 6.5 VDD
UNITS V V
Static Electrical Specifications
LIMITS -55oC, +25oC +125oC MIN 1.5 VDD - 0.1 0.7 VDD MAX 1000 -0.7 0.1 0.3 VDD 10 10 10 7.5 15 UNITS A mA mA V V V V A mA A pF pF VDD (V) 5 5 5 5 5 5 5 5 5 5 -
PARAMETER Quiescent Device Current (Note 1) Output Low (Sink) Current (Note 1) Output High (Source) Current (Note 1) Output Voltage Low-Level Output Voltage High-Level Input Low Voltage Input High Voltage Input Leakage Current (Note 1) Operating Current (Note 1) Three-State Output Leakage Current Input Capacitance Output Capacitance NOTE: IDD IOL IOH VOL VOH VIL VIH IIN IDD1 IOUT CIN COUT
VO (V) 0.4 4.6 0.5, 4.5 0.5, 4.5 0, 5 -
VIN (V) 0, 5 0, 5 0, 5 0, 5 0, 5 0, 5 0, 5 0, 5 -
MIN 2.7 VDD - 0.1 0.7 VDD -
MAX 270 -1.3 0.1 0.3 VDD 2.6 5 2.6 7.5 15
1. Limits designate 100% testing, all other limits are designer's parameters under given test conditions and do not represent 100% testing.
Read Cycle Dynamic Electrical Specifications
tR, tF = 10ns, CL = 50pF LIMITS +25oC, -55oC +125oC MIN 505 MAX 505 505 UNITS ns ns ns
PARAMETER Read Cycle Access Time from Address Change (Note 1) Access Time from Chip Select
SYMBOL tRC tAA tAC
VDD (V) 5 5 5
MIN 360 -
MAX 360 360
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CDP1823C/3
Read Cycle Dynamic Electrical Specifications
tR, tF = 10ns, CL = 50pF (Continued) LIMITS +25oC, -55oC PARAMETER Access Time from MRD (Note 1) Data Hold Time After Read NOTE: 1. Limits designate 100% testing. All other limits are designer's parameters under given test conditions and do not represent 100% testing. SYMBOL tAM tDH VDD (V) 5 5 MIN 50 MAX 310 +125oC MIN 70 MAX 435 UNITS ns ns
tRC tAA ADDRESS tAM (NOTE 1)
MRD
CS2, CS3, CS5 (NOTE 1) tAC CS1, CS4 tDH 90% HIGH IMPEDANCE VALID DATA 10%
NOTES: 1. Minimum timing for valid data output. Longer times will initiate an earlier but invalid output. 2. MWR is high during read operation. Timing measurement reference is 0.5VDD. FIGURE 1. READ CYCLE TIMING DIAGRAM
Write Cycle Dynamic Electrical Specifications
tR, tF = 10ns, CL = 50pF LIMITS +25oC, -55oC VDD (V) 5 5 5 5 5 (NOTE 2) MIN 280 70 70 140 70 +125oC (NOTE 2) MIN 400 100 100 200 100
PARAMETER Write Cycle Address Setup Time (Note 1) Address Hold Time Write Pulse Width (Note 1) Data to MWR Setup Time (Note 1)
SYMBOL tWC tAS tAH tWW tDS
MAX -
MAX -
UNITS ns ns ns ns ns
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CDP1823C/3
Write Cycle Dynamic Electrical Specifications
tR, tF = 10ns, CL = 50pF (Continued) LIMITS +25oC, -55oC VDD (V) 5 5 (NOTE 2) MIN 50 210 +125oC (NOTE 2) MIN 70 300
PARAMETER Data Hold Time from MWR (Note 1) Chip Select Setup NOTES:
SYMBOL tDH tCS
MAX -
MAX -
UNITS ns ns
1. Limits designate 100% testing. All other limits are designer's parameters under given test conditions and do not represent 100% testing. 2. Minimum timing to allow the indicated function to occur.
tWC tAS ADDRESS tAH CS1, CS4 tCS CS2, CS3, CS5
MWR
tWW tDS tDH
BUS 0-7
VALID DATA
NOTE: 1. MRD must be high during write operation. FIGURE 2. WRITE CYCLE TIMING WAVEFORMS
Data Retention Specifications
TEST CONDITIONS +25oC, -55oC PARAMETER Minimum Data Retention Voltage (Note 1) Data Retention Quiescent Current Chip Deselect to Data Retention Time Recovery to Normal Operation Time NOTE: 1. Limits designate 100% testing. All other limits are designer's parameters under given test conditions and do not represent 100% testing. SYMBOL VDR IDD tCDR tRC VDR (V) VDD (V) MIN MAX 2 LIMITS +125oC MIN MAX 2.5 UNITS V A ns ns
2 -
5 5
450 450
100 -
650 650
400 -
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CDP1823C/3
DATA RETENTION MODE VDD 0.95 VDD VDR tCDR tf tr tRC 0.95 VDD
CS VIH VIL
VIH VIL
FIGURE 3. LOW VDD DATA RETENTION WAVEFORMS
R A15
1 2 3
24 23 22 21 20 19 18 17 16 15 14 13
VDD A0 A1 A2 A3 A4 A5 A6 01 A7 A8 A9
R A14 R A13 A12 A11 A10
4 5 6 7 8 9 10 11 12
R = 10k 20%
PACKAGE D
TEMPERATURE 125oC
DURATION 160 Hrs
VDD 7V
0 01
1.6
2.2
5.0
6.6
7.2
10.0 VDD 0 VDD
A0
0 VDD
A1
0
NOTE: 1. A1 - A11 are division by 2 based on A0. FIGURE 4. DYNAMIC/OPERATING BURN-IN CIRCUIT AND TIMING DIAGRAM
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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